By: Raymond P. Cronin
System provides a flexible solution to a challenging problem
The substrates for advanced chip-scale packages have become, in essence, miniature circuit boards with multiple layers of metallization. While substrate testing is now crucial, delivering an electrical stimulus to minuscule test nodes, ramping up for volume runs, and qualifying a diversity of product types has posed a major challenge for the contract manufacturer. Fabricators and industry watchers acknowledge that current production test approaches cannot provide 100% functional evaluations of organic substrates without sacrificing throughput and accuracy.
A recently introduced system by Everett Charles Technologies changes the status quo by incorporating a new technology for substrate test with the versatility to switch back and forth from prototype runs to high-volume production, and the capacity to handle diverse chip-scale types with a pre-fabricated interface. The new ECT system, along with emerging standards for high-density substrate production, will enable laminated chip carriers to be tested as rapidly and easily as traditional printed circuit boards.
Substrate Test Metrics
The challenge in implementing this goal has to do with the pitch and size of test points on the surface(s) of the substrate. Densities include conductor lines and spaces as narrow as 1-2 mils and vias (vertical connections) which are typically 6 mils or less in diameter. The pads are also easily damaged and their integrity must be maintained for wire bonding or device attachment in the next phase of assembly.
Issues like these have resulted in a compromise between pad marking, test quality and throughput in current evaluations of organic chip carrier substrates. Various approaches ranging from isolation test only to flying probe to non-contact capacitive sensors tests have been pursued in the past with unsatisfactory outcomes. The increasing complexity of these substrates, the requirement for production throughput and the accessibility to topside and flip side nodes or nets has impacted all methodologies.
Isolation testing on universal grid testers was originally attempted because these systems were widely available at substrate production sites. While the technique offered significant throughput, it could not provide a test of continuity between grid array pads and the fine pitch device pads. Other methods involving capacitance testing generally resulted in less definitive "implied continuity" ratings. While flying probe testers have been successful in prototyping and limited-run assignments, currently available systems lack the throughput for the high-volume production and cost targets of independent substrate suppliers.
New solutions for test must incorporate modular interfacing and options for rapid scaling to full-volume runs, with fast conversions for other part numbers or prototype assessments. These requirements have been addressed on the ECT system with the following innovations:
Part Flow Considerations
Adhering to industry acceptance for the JEDEC tray, ScanMan is configured to accept standard JEDEC tray loading and unloading while maintaining test speeds. The user has the choice of off-loading failures to a built-in repository or selecting a system-initiated "mark" for failed parts while still returning them to the JEDEC tray with good product. Failed parts may be noted in a software code for another assessment later in the process run.
If the user must detour from a production run to check a prototype substrate, it is generally possible to stay with the same modular interface. The operator backs away the automation assembly, retrieves the robot scanning trace stored in the test system's software, performs the manual test, and re-docks the automation unit, returning to full-speed operation.
Raymond P. Cronin - -- is corporate vice president of the Semiconductor Test Group, Everett Charles Technologies (a subsidiary of Dover Corp.), Pomona, CA. He can be reached at
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