Many of the major ATE manufacturers claim that in-circuit testers find defects directly related to bare-board process faults (either shorts or opens). Shorts and opens may account for as much as 1% to 4% of board test failures.

Finding bare-board faults after assembly and wave solder, instead of finding them at the bare-board level, is a most expensive venture in both time and cost. Many of today's modern loaded PCB products (heavily populated, dual-sided SMT designs) have a manufacturing cost of several thousand dollars, making them a major part of the overall product cost.

Defects at the Board Level

Specifiers of bare PCBs expect their suppliers to deliver boards that are electrically and physically correct, and verified by a final electrical test. Regrettably, this is not always the case.

A 100% electrical test does not necessarily mean the board is defect free. This contradiction is easily explained. There are simply too many reasons that bare-board testing can be deficient:

• The board shop may receive orders that are not explicit (inadequate electrical measurement requirements).
• Test fixtures may not provide 100% fault coverage.
• Shortcuts may be used to generate the electrical test program.

Figure 1	Preventing Failures
	Prevention of bare-board failures can be a simple program. Several options exist for specifiers, purchasers and QC managers to ensure 100% electrical test.
	All test points should be located at the end points of all traces or trace branches (Figure 1). This includes all component holes fed by internal layer connections, all surface-mounted pads with end traces (or associated test pads), and all single-point networks (isolated points).
For boards containing surface-mount pads and/or card-edge fingers that terminate traces on both sides, simultaneous dual-sided access fixturing to verify continuity between sides is required, or voided through-holes will not be detected. Flip testing is not acceptable.

Electrical test parameters must be specified to include:

• Continuity resistance pass/fail threshold (the lower the better, 5 Ohms is practical).
• Maximum continuity test current (the lower the better, prevents damage to board).
• Isolation resistance pass/fail threshold (the higher the better; 100 MOhms is a good test).
• Voltage applied to passing networks during isolation test (100 V, 250 V typical; not as important as isolation resistance).
• Isolation test method (each net to all other nets).
• Any special requirements related to components embedded within the substrate, characteristic impedance or other special features.

Figure 2 provides a summary of these test parameters.

Test programs must be generated from an original CAD net list derived from the original CAD design data base. A second choice is Gerber.

Net list testing is the only method that guarantees 100% electrical test. Limitations of self-learn methods, as well as Gerber net list methods, allow room for error that ultimately shows up in loaded-board test.

Ideally, 100% electrical test is a result of the fixture and test program matching each other and the product as well as very specific test parameters. Automatic board marking of good boards derived from a test-passed signal completes the process (eliminating error-prone manual marking).

Summary
The process of final electrical test of bare PCBs has become more intricate and more important as the complexity of the board increases. Loading very expensive electronic components on defective circuit boards can be costly and potentially catastrophic.

Specifiers who develop a basic understanding of the practical aspects of the real-world test environment can significantly improve their control over the quality of the boards they receive. Loaded-board test yields will improve dramatically when a bare-board electrical test specification is clearly defined.