A True Test of
Chip Carrier Subtrates

Raymond P. Cronin

A new technology that combines a high-throughput scanning mechanism with a standard universal grid test system, offers test characteristics closer to ideal than traditional methods.

The use of organic chip carrier substrates as a critical building block in advanced semiconductor packages is clearly on the rise. While the substrates offer performance and cost advantages, there are significant obstacles preventing the delivery of these emerging devices with assured quality in the quantities desired by the electronics manufacturing industry. One of these significant obstacles has been, and continues to be, the availability of cost-effective testing that does not compromise quality.

The purpose of this article is twofold. First, existing methods of testing carrier substrates are reviewed, with specific examination of the quality tradeoffs relating to each test methodology. The second section of the article describes a recently introduced technology that advances the state of the art in the testing of chip carrier substrates, greatly reducing the tradeoffs mentioned in the first section.

Chip Carrier Characteristics
A number of issues contribute to the complexity of testing single-chip-carrier organic substrates. Table 1 identifies those issues. Ironically, the ability to make such substrates without being able to test them effectively mirrors an age-old issue in the semiconductor industry.

Issue Effect
Pad Pitch (4-10 mils) Difficult to access
Pad Size (2-6 mils) Easily marked and damaged
Pad Use (Wire bond or direct attach) Cannot be damaged; ideally no marking
Connectivity (Fine-pitch pads to each other or power and ground) Need to access fine-pitch pads on an individual basis
High-Speed Performance Need to know resistance levels and do Ohm's Law test with true force of voltage and current to assure quality of electrical connection to the greatest degree possible
Image Registration Relative position of fine-pitch pads can vary greatly from substrate to substrate, making access difficult or requiring alignment technology
TABLE 1: Issues that contribute to complexity of testing single-chip-carrier organic substrates


Two of the most typical organic chip carriers are either double or single sided. The double-sided carrier has a footprint on one side to which the die will be connected. On the second side is the footprint that will be attached to a printed wiring board (PWB). The singlesided carrier has the die on the same side as the footprint that will attach to the PW13. The functional aim of all single chip carriers is to connect each of the fine-pitch device pads to a grid array pad. Typically, the netlist profile is a significant number of two-point networks, power, ground and a few single-point nets. A particular characteristic affecting test results that will be evaluated throughout this discussion of theoretical device tests is the connection of more than one fine-pitch pad to the same network.

From a circuit manufacturing perspective, chip carriers are highly complex devices. The density of the packages results in conductor lines and spaces as narrow as 1 to 2 mils. The vertical connections or vias are typically 6 mils or less in diameter and defined either with photolithography or by use of highly specialized laser or mechanical drills. The complexity of the manufacturing process necessitates electrical test to assure that only functional substrates move upstream to the packaging process. Passing along defective substrates will cause them to be populated with good semiconductor devices, compounding the cost of failure for the package manufacturer.

The Ideal Test
Ideally, electrical test of substrates for continuity and isolation will mirror as closely as possible the actual functioning of the substrate package when populated with a die. Accurate functional testing relies on quality electrical connections exhibiting low node-to-node resistance of less than 10 ohms and high electrical isolation (greater than 10 MegOhms) of networks from each other. Thus. it is necessary that the test process be based on actual flow of current between nodes to measure continuity, and on a forced voltage between networks to measure isolation. Ideally, every network will be tested for isolation and all nodes will be tested for continuity, including fine-pitch nodes on the same network (such nodes are often referred to as "loops").

The difficulty in obtaining the ideal test lies in the pitch and size of the pads on the device footprint. The pitch makes it difficult io physically locate test probes on pads while the small size of the pads makes them very difficult to contact. The pads are also highly susceptible to damage, which is unacceptable, as the device pads must remain intact in order to accommodate a wire bond or direct pad attach. Registration issues contribute to lower test throughput and false test results. These factors have forced substrate manufacturers to make tradeoffs between pad marking, test quality and test throughput in testing single chip carrier substrates.

Glossary of Terms

Chip carrier substrate
The organic laminate carrier layer of the packaging structure

Flying probe tester
Fixtureless test equipment with four or more moving probe heads

Indentation or "pinch" mark left on pad by a test probe

Connectivity of circuitry as defined in design database Pitch Center-to-center distance between adjacent test points on a device

Test pads
Designated points for electronic test probing

Test probe
A metailic contact that connects test points during test

Universal grid tester
System using a rigid pin fixture that accesses a spring-probe bed of nails


Review of Traditional Methods
Traditionally, four methods have been used to test chip carrier substrates:

  • isolation test only
  • flying probe test
  • gang continuity
  • capacitive continuity.

As one might expect, each method has advantages and disadvantages, but none of these techniques meets the requirements of the ideal test.

The simplest test method is isolation test only. Since the grid array pads of the substrate are usually easily accessed with traditional probes, one can test all of the networks connected to those pads for isolation by simply fixturing only those pads. Many manufacturers choose this approach due to its ease and compatibility with widely installed dedicated or universal grid testers. While the technique also offers significant throughput, there is no test of continuity between the grid array pads and the fine-pitch device pads. This is a significant shortcoming and has led to the use of other methods.

Flying probe test offers the advantage of nearly comprehensive test coverage. Many probers are capable of accessing the fine-pitch device pads and thus a true continuity test can be accomplished, although there will be a witness mark left on the test pad and care must be taken not to damage the unit under test. Isolation test with a flying probe is usually based on contacting one point per network and measuring capacitance. While the approach does not quite match the quality of isolation test based on forced voltage between networks, the flying probe technique has gained wide acceptance in certain applications. The greatest disadvantage of the flying probe test is simply the lack of throughput. The typical throughput rate is so low that it is not a practical means of production testing large quantities of chip carrier substrates.

Like isolation test only, gang continuity is usually accomplished with installed opens/shorts test systems. The isolation test is done in a traditional manner, usually prior to continuity testing. Continuity testing is performed using a compliant, conductive material (usually rubber or cloth) to short all of the fine-pitch pads simultaneously. The continuity is thus actually tested from pad to pad in the grid array. Fine-pitch pads (loops) that are connected to the same network will not be tested for continuity. This limitation and the fact that shorting material often makes intermittent contact or leaves a residue have resulted in only sporadic implementation of this technique for testing chip carrier substrates.

The fourth alternative, capacitive continuity, is based on use of specialized test equipment that applies forced voltage isolation tests while using a special sensing technology for continuity testing. A dedicated fixture is built to access the grid array area of the substrate. Isolation testing is done in the traditional manner. The continuity test is accomplished as a sensor is positioned directly over the fine-pitch pad area without making actual electrical contact to the pads. The sensor can detect a signal that is sequentially injected through the grid array area pads. Opens to the finepitch pads are detected by the absence of the injected signal. One shortcoming with this test approach is that continuity measurement is implied and not readily correlated to ohmic resistance. Further, there can be difficulty in validating the continuity of flne-pitch pads connected to the same network (loops).

A New Technology
A new approach delivers on all fronts. There is no marking or pad damage, throughput is high enough to achieve production volume testing, and continuity and isolation testing is based on contact and true resistive measurements. The ScanMan" test system uses the new technology, which combines a traditional universal grid tester and fixture-which tests the BGA footprint of the substrate-with a high-speed ultraprecise robot that "scans" a flexible electrical contact plate over the device attach pads (patent is pending on the process and equipment). The movement of the robot is synchronized with the switching matrix of the grid test system, allowing for continuity resistance measurement of every node. The universal grid test fixture provides excellent contact to the grid area array while delivering an effective cost-per-test point.

The isolation test is done prior to the robot contacting the fine-pitch footprint. A voltage up to 250 volts is applied between all networks on the substrate, achieving a true N2 isolation test. With a voltage applied, every network is measured for leakage against every other network on the substrate. The use of a traditional grid and switching matrix offers the advantage of very high throughput in conducting the isolation test.

Continuity testing is accomplished by synchronizing the tester's switching matrix with the movement of the robot arm. The robot is programmed to move the scanning plate across the surface of the fine-pitch pad array. As the scanning plate sweeps the surface of the pad, a resistance measurement is made, based on the current that is flowing from the tester grid and the fixture through the substrate's grid array pads. In fact, more than one resistance measurement can be made on a given pad, allowing for validation of not only conductor integrity but of the surface of the pad itself.

The scanning plate is a unique contacting mechanism designed to scan the finepitch pad without marking. Life testing conducted on the scanning action indicates that the plate exhibits a self-cleaning action that yields repeatable contact, and marking is imperceptible. Figures 1 and 2 show a magnified picture of pads unscanned (Figure 1) and scanned by ScanMan" 10 times (Figure 2). Figure 3 shows a pad contacted by conventional methods. The superior contact of the plate to the pad under test allows for continuity testing below 5 ohms. The plate is designed to closely follow the terrain of the substrate, easily flowing through the peaks and the valleys present as a result of the device pads and the solder mask surface.

Figure 1: Magnification of unscanned pads.

Figure 2: Magnification of pads scanned by
ScanMan" 10 times.

Figure 3: Pad contacted by conventional methods.

The sweep action is programmed so that thd plate attached to the precise and fast robot arm contacts every fine-pitch pad. A typical sweep action is 1-2 sec. resulting in a total test time of 4 sec. or less. The contact plate is large relative to the pad under test; thus, registration problems are eliminated and the number of false test results is kept to a minimum.

The increasing demand for organic chip carrier substrates is taxing existing test methods in the areas of quality and throughput. Traditional test methods have forced tradeoffs to occur, diminishing test quality. It is imperative that such substrates are tested for continuity and isolation by means of standard Ohm's Law resistance methods. A new technology that combines a high-throughput scanning mechanism with a standard universal grid test system altows for physical contact of all substrate pads without damage and ensures direct measurement of resistance based on Ohm's Law methods of forcing voltages and currents. The new technology offers test cbaracteristics closer to ideal than traditional methods without sacrificing throughput.

Table 2 presents a comparison of traditional test methods, the hypothetical standards of an ideal test and the attributes of the new technology.

  Ideal test New scanning technology Isolation test only Flying probe test Gang continuity test Capacitive continuity
Marking Little or none None None Varies depending on equipment Residue None
Continuity resistance <10 ohms <5 ohms No continuity test <10 ohms > 10 ohms due to intermittent contact No direct measurement
Isolation resistance > 10 megohms > 10 megohms > 10 megohms Capacitive > 10 megohms > 10 megohms
Throughput > 500/hr. > 500/hr. > 500/hr. <50/hr. 100-200/hr. > 500/hr.
Registration issues None None None Optical alignment required Cause intermittent test Cause intermittent test
Test fixture Low cost Universal grid (low cost) Universal grid (low cost) None required Universal grid (low cost) Dedicated (higher cost)
TABLE 2: Comparison of traditional test methods and new scanning technology to ideal test.

Raymond P. Cronin-(603) 432-4528, e-mail: [email protected] corporate vice president of the Semiconductor Test Group, Everett Charles Technologies (a subsidiary of Dover Corp), Pomona, CA.

Reprinted with permission from HDI, June 1999. 1999 MILLER FREEMAN, INC. All rights reserved.


©1998-2003 Everett Charles Technologies. All rights reserved. Everett Charles Technologies, 700 E. Harrison Ave., Pomona, CA, 91767, U.S.A.